The present disclosure relates to computer systems, and more particularly to an inter-processor memory for a multi-processor computer system.
A computing system may include multiple processing devices, each of which may run one or more processes simultaneously. In order to share data between these processes, an inter-processor memory is necessary. Inter-processor information exchange via an inter-processor memory may require relatively high resources in the computing system. There are various types of inter-processor memory available. An inter-processor memory that is implemented as a register array may handle multiple write and read accesses per clock cycle; however, relatively complex control logic may be necessary for the register array. While writes from a process to the inter-processor memory are immediately available to all other processes in a register array inter-processor memory, the physical size necessary for the memory registers and the control logic for such a memory may not be feasible in some computing systems. Other, more resource-conscious approaches sacrifice performance of the inter-processor memory. An inter-processor memory may be implemented as a shared memory with arbitration, which may have a relatively small size, but relatively low performance, as updates to the memory may not be available to all processes at the same time. Other examples of inter-processor memory are a bi-directional first-in-first-out (FIFO) scheme, or as a memory cluster with a crossbar. However, in these memory schemes, there may be a delay before updates from a process are available to other processes.